Curriculum Vitae

Education

03/2015 – 06/2018
Cyprus International Institute of Management (CIIM), Cyprus

Masters of Business Administration (MBA)

Grade: Distinction
Dissertation title: Importing, Promoting and Distributing Novel Products in the Cyprus Market.
Dissertation Grade: 94%
Completed Courses: Financing of New Ventures, Business Ventures-From Idea to Execution, Communication Skills, Competitive Analysis, Corporate Finance, Digital Marketing, Ethics, CSR & Sustainability, Financial Accounting, International Business, Leadership, Managerial Economics, Managing Strategic Change, Marketing Management, Negotiating Skills, Organizational Behaviour, Presentation Skills, Starting a New Business, Strategic Marketing. Quantitative & Qualitative Methods
Fully funded by: Phileleftheros Newspaper.

10/2005 – 10/2008
University of Bristol, UK

Ph.D. in Computer Science (Top 5 Universities in UK)

Thesis title: Novel Fault-Tolerant Techniques for the Improvement of Reliability and Yield in Advanced Technologies (I completed my PhD the 25th month but due to the internal regulations of the University of Bristol, I was not allowed to submit my thesis before the completion of the 33rd month in the program).
Supervisor: Prof. Dhiraj K. Pradhan
Short Description: My thesis was completed in 6 parts.

  • A novel multiple-error correcting technique.
  • A novel SRAM memory design with improved reliability using Built-In-Current-Sensors.
  • An innovative memory design to improve the fabrication yield while reducing the cost per chip.
  • A framework to cope with the reliability and yield trade-off in nanotechnology based circuits.
  • A multiple SEU tolerance FPGA.
  • Algorithmic level fault tolerance technique to cope with long duration transients

Partially funded by: Department of Computer Science, University of Bristol, UK.

More detailed CV may be downloaded here – updated January 2019.

Since 03 Nov 2014 I am a Senior Member of Technical Staff, Reliability Architect at Advanced Micro Devices (AMD) Inc.

Before this I was a Validation Engineer at Intel® Corp in Barcelona, Spain. I am responsible for planning and performing the validation strategy of different parts of the core of the recently announced Intel co-processor family XEON Phi™.

Additionally to being a Validation Engineer at Intel Corp i was also acting as a research associate at the Computer Architecture Group of Universitat Politècnica de Catalunya BarcelonaTech.

I am also founder and governing body member of C. A. EVOLVIT LTD aka evolvI.T. which stands from evolve I. T. and is specialised in the design and implementation of web applications and software for different companies. It also offers  I.T. consulting services  to companies and participates in research projects with academic partners and research centers.

Some time ago i was post-doctoral researcher at the University of Bristol (UoB) in the Department of Computer Science (CSD) working on a project funded my the Research Promotion Foundation (RPF), Cyprus in collaboration with the Department of Electrical and Computer Engineering of  the University of Cyprus, Department of Electrical Engineering and Information Technology of  Cyprus University of Technology and SignalGeneriX. My current research project is in the area of reliability and Manycore chips with title “System Validation via Intelligent Collaboration for Reliable Next-Generation Manycore Chips “.

I have successfully defended my PhD at the UoB in the CSD with title “Error Tolerant Techniques for the Improvement of Reliability and Yield in Advanced Technologies” under the supervision of Prof. Dhiraj Pradhan. During my PhD I collaborated with different scientists and published more than 30 technical papers in different conferences and workshops among them DFT, ETS, VTS and VLSID and won a best paper award .  My publication list may be found here. For the pdf version of my papers please refer to ieee explore website.

Prior to the PhD I completed an MSc in Advanced Computing and in particular on “Global computing and Multimedia” again in the University of Bristol. My thesis was entitled “A Novel Soft Error Tolerant Low Power RAM Architecture” and was conducted under the supervision of Prof. Dhiraj K. Pradhan. It was published in the “Proceedings of the 20th Annual Symposium on Integrated Circuits and System Design SBCCI ‘07″ ISBN:978-1-59593-816-9 page(s) 300-305. While a master’s student I was awarded with a scholarship from Misys foundation. For my bachelor’s degree I found myself in the capital of the former Soviet Union, Moscow. My undergraduate studies focused on the field of Computer Science and Informatics, at the Moscow Power Engineering Institute Technical University (MPEI-TU). At the end of my studies at MPEI (TU) I was classified in the top 10 students with excellent performance. Further details regarding my PhD and educational background may be found here.

I was a Research Fellow in the Sensors Research Laboratory (SRL) of the School of Engineering at The University of Warwick working on a project about “Nano Structured micro Power Smart Gas Sensors”.

Additionally, I was the founder of Net-Twister LTD. Net-Twister LTD was specialised in the design and implementation of websites and software for different companies.

Moreover, during my studies in Bristol I was employed by the university as a teaching assistant at several courses in the department of Computer Science and while in Moscow I was a lab assistant at MPEI (TU). I was a teaching assistant at the course “Fault Tolerant Computer Design (COMSM30125)” for 3rd year undergraduates and at the course “Introduction to Computer Architecture (COMSM1302)” for the postgraduates of the “MSc in Computer Science: Conversion course” last semester. More details about my working experience may be found here and about the courses may be found here and here respectively.

I am proud to be able to communicate into three languages(greek, english and russian).

Further details regarding my PhD and my educational background may be found here (education subsection) and my publication list here.

Details about my working experience is available here (work experience subsection).